Publication: An FPGA implementation of 2-D CNN Gabor-type filter
dc.contributor.author | Saatçı, Ertuğrul | |
dc.contributor.author | Cesur, Evren | |
dc.contributor.author | Tavşanoğlu, Vedat | |
dc.contributor.author | Kale, İzzet | |
dc.contributor.authorID | TR10488 | tr_TR |
dc.contributor.authorID | TR36339 | tr_TR |
dc.date.accessioned | 2016-04-22T12:53:00Z | |
dc.date.available | 2016-04-22T12:53:00Z | |
dc.date.issued | 2007 | |
dc.description.abstract | A field programmable gate array (FPGA) implementation of the Gabor-type filter is presented. The implementation uses the forward Euler approximation with optimal step size to solve the CNN cell-state equation. The FPGA is implemented on Xilinx Spartan XC3S400 device using 219 slices. An image of dimension 60 x 60 can be processed without using any external RAM only with the block RAM. | tr_TR |
dc.identifier.uri | http://hdl.handle.net/11413/1111 | |
dc.identifier.wos | 258708400071 | |
dc.language.iso | en | |
dc.publisher | IEEE, 345 E 47TH ST, NEW YORK, NY 10017 USA | |
dc.relation | 2007 EUROPEAN CONFERENCE ON CIRCUIT THEORY AND DESIGN, VOLS 1-3 | tr_TR |
dc.title | An FPGA implementation of 2-D CNN Gabor-type filter | tr_TR |
dc.type | Article | |
dspace.entity.type | Publication | |
local.indexed.at | WOS |
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